New MCUs, DSPs and FPGAs target SBCs

By: lw

Late June normally is considered the beginning of the summer dog days, when semiconductor vendors’ marketing departments hide until Labor Day, while sales arms focus on shipping the products sampled early in the year. This year, however, a cavalcade of intriguing MCU, DSP, and FPGA architectures are being launched that explicitly target the single-board computer market. Freescale Semiconductor has taken the widest approach by updating QorIQ (Power Architecture), ColdFire, and ARM families simultaneously – an ambitious agenda that may be related to the June 22 opening of the Freescale Technology Forum. Still, that can’t explain the simultaneous rollout of Octasic’s 2200 DSP, or Xilinx’s three new families of 28-nm FPGAs. It’s just a busy time on the chip front, and that means a bevy of new choices for embedded boards.

Freescale has the trickiest balancing act to perform. It wants to show the world that its ARM licensing is broad-based, while emphasizing to high-end embedded customers that the Power RISC architecture (from PowerPC) will not go away. Last year, Freescale updated the PowerQUICC with a new multicore family of Power derivatives called “QorIQ” (pronounced “Core IQ”, and don’t ask). This year, Freescale is launching the P3 and P5 members of the QorIQ family, with the P5 being particularly unique in being the first to offer 64-bit addressability – which product marketing director Katie Eckermann said was implemented as much to expand addressable memory space as for raw performance. The P5 is based on the e500 core.

The two instances of P5 – the 5010 and 5020 – are aimed at SBCs in mil/aero and robotics applications, featruing dual 64-bit cores, high-speed serial interface ports, and a CoreNet coherent switching fabric internal to the MCU. Lest we forget in all the excitement, the P3 is no slouch. It’s a power-efficient spin of the existing P4 architecture and offers four 32-bit e500mc cores with CoreNet and Hypervisor features preserved from P4.

In early June, Freescale updated its popular ColdFire architecture with the ColdFire+ 90-nm product line. The most interesting common aspect of ColdFire and ARM products is that they use a special thin-film storage flash, which replaces traditional nonvolatile memory with a thin-film block that is lower power, higher performance and cheaper to produce. ColdFire+ has emphasized mixed-signal blocks, power control and analog functionality to increase the controller’s use in sensor and factory-floor applications.

And then there’s Kinetis, which represents Freescale’s latest family using the ARM Cortex-M4 core. This product got introduced June 22 at FTF, and Freescale promised more than 200 Kinetis products in five family groups – K10, K20, K30, K40 and K60 – with various combinations of LCD control, USB interfaces and Ethernet MACs. Freescale is touting the ColdFire+ Qx and Jx families as appropriate for industrial and consumer apps, with on-chip encryption and hardware random-number generation, while the Kinetis ARM-based family fits in at the high end of industrial, with automotive applications favored, as well. Freescale offers a common hardware development platform for its MCUs which it calls the “Tower System,” with a controller board sitting on top of a 3D rack.

If that isn’t enough activity, Octasic launched its 2200 family of the Opus asynchronous DSP architecture this week. With 24 DSP cores and interfaces that include Serial RapidIO, Serial Gigabit Ethernet and PCI Express, the board-level applications are obvious. But Octasic has segmented this application space into wireless gateway, base station and session border controller cards which would use the Opus 2224W chip; and media/wireline cards in applications such as media gateways, where the 2224M chip would be preferred. The company is out to prove that, when asynchronous DSP cores are utilized, the elimination of clock trees and reduced capacitance means that multicore DSPs remain strong contenders against MCUs or FPGAs with DSP blocks integrated on board.

Not to be outdone, Xilinx is driving head-on into MCU and DSP accounts by getting rid of the Virtex/Spartan bifurcation that characterized past architectures. Xilinx will offer three families based on 28-nm processes: an Artix-7 that is equivalent to Spartan while cutting footprint and power in half from Spartan-6; the Kintex-7 family, which offers performance equivalent to the Virtex-6 with half the cost and power dissipation; and the new high-end Virtex-7, 2.5 times as big in gate count as Virtex-6, with up to 2 million logic cells and a serial bandwidth of 1.9 Terabits/sec.

All the product families can take advantage of complex MCU and communication cores. Patrick Dorsey, senior director of product management at Xilinx, said that a new kind of high end already was being defined in Virtex-6 for products that offered transceivers capable of supporting 40- and 100-Gigabit Ethernet. As the ultra-high-end clamors for new products with ultra-fast transceivers and complex logic, it made sense to split the former Virtex family into two, with different performance requirements and price points.

So there you have it, SBC developers. A single week in MCU territory has given you enough new architectures to make your job of comparing embedded instruction sets exponentially tougher. What more can we expect prior to Labor Day?